Computer systems have historically employed a two-tier storage model, which includes a fast, byte-addressable memory (i.e., a volatile memory) device that stores temporary data that is lost on a system halt/reboot/crash, and a slow, block-addressable storage device (i.e., a non-volatile memory device) that permanently stores persistent data, which can survive across system boots/crashes.
Volatile memory devices (also referred to as synchronized memory devices) and non-volatile memory devices (also referred to as asynchronized memory devices) have different timing parameters and employ different communication protocols, which make it difficult to combine the two types of memory devices in one memory space controlled by a single controller. For example, volatile memory devices (such as dynamic random access memory or DRAM) use fixed timing for performing their respective operations (e.g., read/write), while non-volatile memory devices (such as flash memory chips) use variable timing for performing various operations. Non-volatile memory devices are also used in transaction based systems that involve frequent handshakes between the controller and memory device. However, using a volatile memory device in such an environment is generally not efficient as the frequent handshakes lead to reduced bandwidth.
The above information disclosed in this Background section is only for enhancement of understanding of the invention, and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.